The OPERATIONAL TRANSCONDUCTANCE AMPLIFIER-capacitor ((OTA)-C) filter is one of the best structures for implementing continuous-time filters. It is particularly important to design a universal (OTA)-C filter capable of generating the desired filter response via a single structure, thus reducing the filter circuit power consumption as well as noise and the occupied space on the electronic chip. In this study, an inverter-based universal (OTA)-C filter with very low power consumption and acceptable noise was designed with applications in bioelectric and biomedical equipment for recording biomedical signals. The very low power consumption of the proposed filter was achieved through introducing bias in subthreshold MOSFET transistors. The proposed filter is also capable of simultaneously receiving favorable low-, band-, and high-pass filter responses. The performance of the proposed filter was simulated and analyzed via HSPICE software (level 49) and 180 nm complementary metal-oxide-semiconductor technology. The rate of power consumption and noise obtained from simulations are 7.1 nW and 10.18 nA, respectively, so this filter has reduced noise as well as power consumption. The proposed universal (OTA)-C filter was designed based on the minimum number of TRANSCONDUCTANCE blocks and an inverter circuit by three TRANSCONDUCTANCE blocks ((OTA)).

A novel low-voltage two-stage OPERATIONAL AMPLIFIER employing resistive biasing is presented. This AMPLIFIER implements neutralization and correction common mode stability in second stage while employs capacitive dc level shifter and coupling between two stages. The structure reduces the power consumption and increases output voltage swing. The compensation is performed by simple miller method. For each stage an independent commonmode feedback circuits has been used. Simulation results show that power consumption is 2.1 mW at 1 V supply. The dc gain of the AMPLIFIER is about 70 dB while its output swing is as high as around 1.2 V.

With advancement of integrated circuit technology and aggressive scaling into nanometer regime, statistical variability in device electrical characteristics caused by discreteness of charge and fabrication process variations has significantly increased. These variations in turn result in fluctuations in output characteristics of important analog building blocks and in particular, AMPLIFIERs. In this paper, with the aid of Monte-Carlo simulations for a TRANSCONDUCTANCE AMPLIFIER and using 1000 different compact models of MOSFET transistors in 35nm technology node, statistical variations of important circuit parameters are investigated and analyzed based on their statistical distributions. Moreover, statistical correlations between circuit parameters are extracted. Analysis of statistical variations for circuit parameters and their correlations has a direct impact on reduction of cost and time of a design and thus, is of great amount of significance.

The performance of a non-coherent UWB receiver with Binary pulse position modulation is simulated with MATLAB; taking into account the effect of nonlinearity, noise, pulse shape and channel effects. This simulation examines the minimum requirements for LNA, AGC, squarer, and OPERATIONAL TRANSCONDUCTANCE AMPLIFIER in analog front-end for sensor network application with 100Kb/s data rate and 10-3 BER. The linearity requirement in (OTA) is achieved using Gilbert cell (OTA) with the technique of multiple gated transistors. For sensor network applications, analog front-end modules must have 4dB NF (Noise figure),-12dBm IIP3, 50dB gain and-75dBm sensitivity for 100Kb/s data rates. The transceiver power consumption is assumed to be below 50mW. The performance of energy detection non-coherent receiver is simulated in Simulink of MATLAB, it shows that BER of Gaussian pulse is lower than doublet and 4 th Gaussian pulse. By increasing the number of transmitted pulse per bit and IIP3, the performance of receiver is improved.

This paper is based on analysis of a common source-common gate low noise TRANSCONDUCTANCE AMPLIFIER (CS-CG LNTA). Conventional noise analyses equations are modified by considering to the low output impedance of the sub-micron transistors and also, parasitic gate-source capacitance. The calculated equations are more accurate than calculated equations in other works. Also, analyses show that the noise of the tail transistor, which is utilized to bias the common gate transistor, will limit noise canceling advantages. So, the common gate transistor is biased by a resistor. That leads to a significant improvement in noise figure. By utilizing a Taylor series expression, a closed-form equation is obtained to calculate IIA3 for the first time. Finally, based on the calculated equation a design procedure is proposed.

The study of low power wireless radio systems is an area in modern defense that especially deals with higher performance filters. In recent years, Gm-C filters have drawn attention due to their high frequency performance and integrability. In this paper, a fourth-order low-pass Gm-C filter with on-chip automatic tuning circuit is presented. The core of this filter is a low-voltage high-frequency CMOS inverter-based OPERATIONAL TRANSCONDUCTANCE AMPLIFIER ((OTA)). To improve the linearity of the (OTA), a new common-mode feedback (CMFB) circuit is presented that is combined with a common-mode feedforward (CMFF) circuit. Moreover, a new automatic tuning circuit is presented. By tuning the bulk voltage of transistors, this circuit compensates the effects of mismatches and temperature changes on the (OTA), and therefore, on the filter cutoff frequency. Furthermore, this circuit consumes small portion of the power consumed by the filter. The circuits are designed and simulated in Cadence using TSMC 90nm CMOS technology and a 1 V power supply. The post-layout simulation results show that the DC differential gain, common-mode gain,-3 dB cutoff frequency and unity-gain frequency of the (OTA) are 34. 7 dB,-26 dB, 255 MHz and 13. 8 GHz, respectively. The cutoff frequency of the filter is 1 GHz, and by applying 0. 2 Vp-p input voltages, the third-order intermodulation (IM3) of the filter at the cutoff frequency is-38 dB. The power consumption and the area of the filter are 4. 8 mW and 0. 043 × 0. 038 mm2, respectively. Moreover, Monte Carlo simulations show the good robustness of proposed filter against the process errors.

A novel gain boosted folded cascode Op-Amp using simple single stage auxiliary AMPLIFIERs is presented. The proposed auxiliary AMPLIFIERs are designed in a way that have proper input and output DC common mode voltage without using common mode feedback network. The inputs of the auxiliary AMPLIFIERs are insulated by the coupling capacitors and floating-gate MOS transistors. Thus, the DC input voltage level limit has been removed. Diode connected transistors are also used in the output of the auxiliary AMPLIFIERs, which keep the output voltage level at the desired. A simple single stage auxiliary AMPLIFIER imposes fewer poles and zeroes on the main AMPLIFIER compared to more complicated AMPLIFIERs where consumes also less power consumption. Simulation results in a 0.18μm CMOS technology show a DC gain enhancement of about 20dB while output swing, slew rate, settling time, phase margin and gain-bandwidth retain almost as the same as previous folded cascode design.

High gain Balun-low-noise-AMPLIFIER (LNA) is proposed for tuner of digital televisions (DTVs). The proposed Balun-LNA is based on CS-CG (common-source-common-gate) structure. To improve the isolasion and frequency response, Balun-LNA has cascode transistors before load resistors. Balun-LNA uses current-bleeding circuit to increasie TRANSCONDUCTANCE of CS transistor, so that current-bleeding transistor has TRANSCONDUCTANCE of N-1 times larger than TRANSCONDUCTANCE of cascode transistor. Thereby, TRANSCONDUCTANCE and current of CS transistor are increased N times, as N-1 times of current pass to current-bleeding transistor. Therefore current of CG and CS stages stay identical. Also, Balun-LNA employs a positive feedback to satisfy input impedance matching and CG transistor has higher TRANSCONDUCTANCE. By increasing TRANSCONDUCTANCE of CS and CG transistors, the proposed Balun-LNA achieves to high voltage gain. Accordingly, CG and CS tansistors have symmetrical currents and loads at the differential output of the proposed Balun-LNA. Symmetrical loads cause the balanced differential outputs. This proposed Balun-LNA is designed in 90-nm CMOS technology and covers the frequency range of 40 MHz to 1GHz. This Balun-LNA achieves the voltage gain of 22.6 dB, S11 of less than -10 dB and the Minimum NF of 5 dB. This Balun-LNA operates at the nominal supply voltage of 2.2v.

Successive approximation register (SAR) analog to digital converter (ADC) architecture comprises submodules such as comparator, digital to analog converters (DAC), and SAR logic. Each of these modules imposes challenges as the signal makes transition from analog to digital and vice-versa. Design strategies for optimum design of circuits considering 22nm FinFET technology meeting area, timing, power requirements, and ADC metrics are presented in this work. OPERATIONAL TRANSCONDUCTANCE AMPLIFIER ((OTA)) based comparator, 12-bit two-stage segmented resistive string DAC architecture, and low power SAR logic are designed and integrated to form the ADC architecture with a maximum sampling rate of 1 GS/s. Circuit schematic is captured in cadence environment with optimum geometrical parameters and performance metrics of the proposed ADC are evaluated in MATLAB environment. Differential nonlinearity and integral nonlinearity metrics for the 12-bit ADC are limited to +1.15/-1 LSB and +1.22/-0.69 LSB respectively. ENOB of 10.1663 with SNR of 62.9613 dB is achieved for the designed ADC measured for conversion of input signal of 100 MHz with 20dB noise. ADC with sampling frequency up to 1 GSps is designed in this work with low power dissipation of less than 10 mW.

In this paper an ultra-low power two stage improved OPERATIONAL trans_conductance AMPLIFIER based on folded cascode is designed. The proposed OPERATIONAL trans_conductance AMPLIFIER operates in weak inversion region. The use of two folded branches in the signal amplification path for the first stage and the new feed_forward compensation path with low bias current on the second stage in this proposed AMPLIFIER increases the DC gain, unity gain frequency, slew rate and decreases the input referred noise. The simulation results in a TSMC 0. 18μ m CMOS technology it shows that the proposed OPERATIONAL trans_conductance AMPLIFIER has unity gain bandwidth of 117 KHz, and consumes 195 nW power from a 0. 6 V supply voltage with DC gain of 101. 4 dB.